1. Field of the Invention
The present invention relates to a high frequency switching circuit which performs amplification, switching, or the like of a signal in a mobile communication apparatus or the like, and a semiconductor device in which this high frequency switching circuit is integrated on a semiconductor substrate.
2. Prior Art
A conventional high frequency switching circuit comprises FETs 101 through 104, and 109 through 112, resistance elements 201 through 204, 209 through 212, 250 through 253, and 256 through 259, first through third signal input/output terminals 501 through 503, and first and second control terminals 610, 620 as shown in FIG. 10.
In this high frequency switching circuit, the first control terminal 610 is connected to the third signal input/output terminal 503, and the second control terminal 620 is connected to the second signal input/output terminal 502, so that a bias voltage is applied to the FETs 101 through 104, and the FETs 109 through 112 (for example, refer to Japanese Patent Application Laid-Open No. 2002-232278 (Page 13, FIG. 6)).
In this configuration, when a signal level supplied is relatively as small as about 20 dBm, sufficient high frequency characteristics can be obtained.
However, in the conventional configuration described above, it is necessary to make voltages of the first and second control terminals 610 and 620 higher as the signal level supplied becomes larger. Incidentally, since an excessive reverse bias is applied to gate-source and gate-drain of each of off-state FETs for a long time, it takes time for the FETs to become an on-state from an off-state. As a result, there has been a problem that a rising edge of an output waveform is rounded.
The relationship between the timing of the signal and the voltage in the high frequency switching circuit in FIG. 10 is shown in FIG. 11.
FIG. 11(a) shows a timing chart of electric power supplied to the second signal input/output terminal 502, and a communication mode of a time division multiple access (TDMA) is assumed. For example, in the case of a GSM (Global System for Mobile Communication) mode, one slot is assigned to transmission and reception, respectively, for a terminal among time slots separated into eight slots. A span of each slot is 577 microsecond.
There is shown a situation in FIG. 11 as an example where after performing transmission between time t2 and time t3, reception is performed at either slot between time t3 and time t6, and transmission is performed again between time t6 and time t7.
FIG. 11(b) shows a timing chart of the voltage of the first control terminal 610 (first control signal), and there is shown a situation where the FETs 101 through 104 for transmission are turned on before transmission is performed (time t1), and the FETs 101 through 104 for transmission are turned off after the transmission is completed (time t4).
FIG. 11(c) shows a chart of the voltage of the second control terminal 620, and it will be understood that a control signal with opposite phase to the signal shown in FIG. 11(b) is applied. As shown in FIG. 11(b), 5 V is applied upon transmission and 0 V is applied except upon transmission as a drain-source bias of the respective FETs 101 through 104 in FIG. 10. Accordingly, a voltage of −5 V is applied to drain-gate and source-gate of the respective FETs 101 through 104 except upon transmission as shown in FIG. 11(d).
Thus, in order to achieve an off-state, a high reverse bias state is maintained, as a result, there causes a problem that it takes long time for the FETs to completely turn on when changing to an on-state next, thereby generating a phenomenon that a rising edge of a transmission waveform is rounded.
FIG. 11(e) shows a chart of electric power supplied from the first input/output terminal 501, and it is shown that the output waveform is rounded.
In FIG. 11(d), a slash portion shows a product of the bias voltage of the FETs 101 through 104 and the time (bias voltage and time product), and the smaller the area is, the further the waveform can hardly be rounded. Incidentally, symbol P1 in FIG. 11(a) shows input power, symbol P2 in FIG. 11(e) shows output power, and (P1−P2) is equivalent to insertion loss of the high frequency switching circuit.